More ChipKit spectrum analyzer progress


Modifications to the ADC

I’ve been able to make solid progress on the spectrum analyzer tonight.  I’ve continued using the ChipKit, I’m fairly happy with it at the moment.  As I mentioned in the last post, I’ve increased the baud rate on the serial port to 115200 baud.  That seems to be the point where the SPI bus speed and the serial port speed are about matched.  There’s still plenty of room to increase it, however.

I’ve been progressing in the project by adding one module at a time, and testing as best I can.  I’ve got PLO2 (mostly) working, and DDS1 seems to be rock-solid.  I’m able to command it to any frequency I want between almost 0 Hz up to 20 MHz.  Tonight, I added the ADC to the list of modules that seem to be working.  To accomplish this, I had to make two modifications to the ADC.  The first was to change it to work with a 3.3v DC supply.  This change was trivial, it’s the same as the modification to run off of the power from the PDM.  You just remove the old voltage regulator and replace it with a bit of wire.  This is necessary because, if it’s powered with 5 volts, the minimum voltage required to mark a digital ‘1’ is 3.8 volts.  The PIC32 in the chip kit is powered by 3.3 volts, so there’s no way that’s going to happen.  In reality, it’s probably going to work, but it’s likely going to give you a headache.  Finally, I removed the two transistors that were on the outputs of each ADC.  They were there to provide stronger output drivers (the ADCs can only drive their outputs with 500uA).  The parallel port requires a pretty healthy amount of current on the status lines.  Because it’s being connected directly to a micro controller, these drivers aren’t necessary.  Not only that, but they were acting as it they were damaged.  With them gone, everything seems to work great!

Now that the ADC and a DDS works, I can begin to use it as a spectrum analyzer… even if it’s only for a very small range of frequencies.  For example, I can make a plot of the filter used with the “squarer” in the DDS:

DDS1 squarer response

It’s not immediately clear whether this plot makes any sense, I’m hoping that I can get someone in the panel of experts to weigh in on it.  It’s reasonable clear that there is a pass band centered around 10.7 MHz, which is what I want.  I’m not sure what to think about those steep slopes and the large spike of to the right.  None of this may matter, as the DDS will never be tuned out there anyway.  It could even be that a harmonic of the DDS output is getting through the passband when it’s tuned there.  I really have no idea.

The plot below is from the final resolution bandwidth filter (RBW) that’s used to set the resolution of the analyzer as a whole.  I got this filter from one of the MSA experts (thanks, Sam), and I know it performs better than this.  Again, I’m wondering if it has this shape due to some quality of the DDS output, or some other factor.

Shape (maybe) of my final resolution bandwidth filter

Ultimately, I think these graphs are great, and very encouraging.  Even if they’re a bit confusing, it’s nice to be able to put something up on the screen.  You might be wondering how I produced them?  Well, that’s the embarrassing bit.  My cheesy analyzer program (which is really just a way to test the suite of classes I’ve written for communicating with the modules) will spit out text that can be used as a CSV (comma separated values) file that can be read by Excel or Numbers.  I used Numbers to create these plots.  I think they’re log-scale plots, because the log detector module produces logarithmically increasing voltage given increasing input power, thus I used linear scaling on the Y axis.  The Y axis is the raw value from the ADC, and the X axis is the frequency.

Update:

I got an email back from Scotty about the graphs I got from my DDS sweeps.  The first plot, of the DDS squarer, is normal.  The reason it has that shape is best explained in the context of the schematic of that part.

DDS Squarer (section of the schematic from scotty’s webpage)

Trace the signal from “OUTA,” it goes through matching network (I think!), then a crystal filter (XF1), and a logic inverter.  Basically, the inverter will “snap” on or off once the sine wave from the filter passes a threshold voltage.  Once the signal is attenuated to a certain level by the crystal filter, the inverter will no longer trigger.  This is the reason for the sharp skirts on either sides of the passband.

Scotty also thinks that the response plot from the RBW filter is indicative of a mismatched input or output.  I’m pretty sure it isn’t the actual filter, so I’m going to look into other sources of impedance mismatch.

Update 2:

Not only did Sam agree that the shape of the RBW filter is likely due to the impedance mismatch between the source and the filter, but that I could probably help the situation with an attenuator.  I inserted one (with a DC blocking capacitor) between the DDS source and the filter, the plotted it again.

Second plot of the filter shape

My only concern now is that the filter bandwidth looks much much wider than I expected.  I don’t know what the cause of this is.  Because I really have no calibration, I don’t know how the “counts” in the ADC map to dBs of signal.  Typically, filters are defined by the points to the right and left of the center that are 3dB “down” from the center level.  However, I may be able to glean some knowledge from the datasheet.

RSSI voltage vs. input power level (from the Analog devices datasheet)

The slope is ROUGHLY(!) a half a volt per 20dB.  I’ll do a better calibration when the code is there, but for now let’s just continue on.  Once we know what the slope is, we need to map the counts on the ADC output to volts.  I’ve converted the ADC to use 3.3volt power, and it’s a 16 bit device, so there are 65,536 counts (numbers) spanning 3.3 volts, or 19859 counts per volt.  In my spreadsheet, I just made a new column that performs this conversion.  Finally, because it looks like 2 volts maps to about 10dB.  So, I added another column to the spreadsheet, this time subtracting 2 from the volts, divide by .5 and multiply by 20.

Unfortunately, it’s not easy to see where the 3dB points are.  Looking at the raw data, I can see that the maximum value is -13.0 dB, so the 3dB points are where -16.0 dB is crossed on each side.  On the low side, it’s 10.6989, and on the high side, it’s 10.701360.  The resulting 3dB bandwidth is .002 MHz, or 2 kHz.  This is exactly the published value.  I guess this means that it was a very successful experiment.

 

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  1. #1 by Underfaze on March 26, 2012 - 6:35 pm

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    Thank you!

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  3. #3 by hpux735 on March 27, 2012 - 10:55 am

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