The PLOs are the work horse of the spectrum analyzer (in my opinion). There are a total of 3 that make it work (assuming that you’re using the Tracking Generator option). (A tracking generator is a signal, generated inside the analyzer, that can match the frequency under investigation. It is useful, for example, to test and evaluate filters.) Two of those 3 PLOs are identical. One is intended for for the analyzer itself, and the other of the pair is for the tracking generator. The third PLO (actually PLO2) is shared between them. This is the PLO that is pictured above. PLO2 is distinct because it uses a passive loop filter, which means that it doesn’t have an amplifier. That is the reason for the unpopulated area in the center-bottom of the PCB as pictured. The reason PLO2 is passive and PLOs 1 & 3 are active is that the control voltage for the oscillator in PLO2 is relatively small, compared to the others.
There were several change orders for these PCBs, and I’ll discuss the ones that apply to all of them first, then dedicate a section specific to the testing and integration of each.
The first required change is disabling an incorrect via to ground. This via is accessible most easily by drilling it out (by twisting a small bit by hand) on the ground side. In the above picture, it can be seen just below the center pin of J1. Notice that the through plating is clearly separated from the ground plane.
The next change includes the addition of several vias to ground. The trace segment pictured here needs 4 to be added. Mine are in slightly different locations that the recommended ones, mostly for convenience. I wanted to do them on straight line segments, rather than the angle. There are a few more that are required as well. See the ECO file. For all these modifications, make sure they still apply to your board. Another change from the recommendation is that I didn’t drill through the trace itself, rather near it. This is because I just wanted to tie the existing trace to ground, not potentially disrupt it.
This is the result of the addition of ground straps. I scraped off the solder mask near the holes, and took a small bit of solid core wire, bent it into a ‘Z’, and soldered it to both sides.
The one exception to this method was on the voltage regulator. I just bent the wire into a “U” and soldered it on the ends as well as the middle.
This is an image of the bottom side of the ground straps, showing the ‘Z’ bends. Also, notice on the right that the previously drilled-out via is now filled in with some CA (Cyano-Acrilate or “super” glue). This is to ensure that it isn’t re-connected when the coax is soldered on.
Wow, I just noticed that I missed ECO #3. This has the effect of making some decoupling capacitors worthless. I’ll have to carefully drill this out while it’s mounted in the frame. Trust me, these changes are a lot easier to make early…
I’ve integrated and tested PLO2. I started with this one because it only depends on the master oscillator, not the DDSs. I figured this would be an easier place to start with fewer failure modes. This would build my confidence, and provide a frequency source I can mix with other PLOs later for testing. Setup was rather simple, but I did have a problem visualizing the output waveforms. I’m certainly not going to be able to post a nice picture of a sinewave. I was able to measure the frequency output, however. My frequency meter claims the output is about 930 Mhz. (for the record, my oscilloscope tops-out at 350 Mhz.) The displayed signal strength was not great, though I’m not sure the frequency counter has a meaningful power meter anyway. Also, I’m still using an oscilloscope probe as an input to the frequency meter.
Update 5/6/2010 9:20 PM:
After some more analysis, I determined that the frequencies I was seeing from PLO2 started at about 910 Mhz, and would slowly increase to about 950 Mhz over the course of about a half hour. I decided to check the voltage of the VCO (Voltage Controlled Oscillator, the heart of the PLO) control line. This voltage was only about .4 volts. This is the reason that the frequency of the device was so low. It was essentially being commanded to the lowest value. This said to me that either there was a problem with this part of the circuit, like some current is being shunted to ground, or there is something wrong with part of the PLL chip. The first thing I did was to check the circuit, there was very high resistance to ground and everything seemed fine. Then I decided to make sure that the RF inputs to the PLL chip were present. They were, the master oscillator and VCO output looked fine.
At this point, I didn’t know what was going on, and I asked on the mailing list. Sam mentioned that the problem I was having sounded like what happens when the PLL isn’t getting commanded with a desired setting. Following this line of reasoning, I attached the logic analyzer to the digital inputs to the PLL.
In the screen shot of the logic analyzer, notice that the “Latch Enable” (or LE) signal is never toggled. The clock and data lines look perfect. I became worried that I was in the same situation as I was with the ADC (a latch output was fried), and I still don’t have replacement latch chips. I attached the oscilloscope to the LE line and there was nothing. No signal at all, not even a degenerate one. I knew that last time I had a problem with the latch I looked at every signal using Sam’s control board test program and they looked fine. I disconnected all the modules from the control board and ran it again.
This is the logic analyzer output using the control board test app. You can see that all the signals appear to be functioning. I even looked at each of these signals with the oscilloscope, still fine. Now, I’m wondering if I have things wired incorrectly. I double checked the logic wiring, and it’s correct.
Since I started the control board tester, I had closed the spectrum analyzer program. I don’t normally do this, because it takes a long time for the source code to be compiled. With everything hooked up, and started the analyzer program, and PLO2 seemed to be working!!! Galvanized by this, I did another dump of the logic connection to the PLL chip. To attach the test leads to the PLO, I had to disconnect the wire header. When I re-attached it, the PLL was acting weird again. And, the logic analyzer was still not displaying the LE signal. This time, I decided to leave everything hooked up exactly as it was, and re-start the application. Again, the module was working! Now, I think I’ve uncovered the problem. I think that the LE signal isn’t being asserted by the program. It seems like if the program starts with everything hooked up it doesn’t matter, but it you just ‘halt’ the scan and make changes, it doesn’t work. I’m not sure if fixing the problem with LE in software will help this, but it’s nice to know that re-starting the app can help some problems.
Finally! PLO2 producing correct output!
I’ll add PLO 1 & 3 soon. Stay tuned.