Posts Tagged Spectrum Analyzer

BladeRF first impressions

BladeRFI recently got a pair of the Nuand BladeRF SDR transceivers, and I’ve got about a days worth of experience with them.  Of course, first thing’s first, I had to print the BladeRF Coaster by Piranha32.  This is especially so because there are a few large tantalum-looking capacitors on the bottom.  Before I had this printed, I used some small machine screws with bolts and made a quick set of standoffs.  The package came with a nice blue USB3 cable and a pair of SMA jumpers; I assume these would go to their transverter, which I don’t have, but they’re nice to have anyway.  There aren’t any instructions in the box, but for a product like this the assumption is that the user knows what they’re getting and how to use it.  This is a reasonable assumption, and I had no problem finding all the relevant documentation.

I’m an ardent mac user, and this sometimes poses a problem while using specialized hardware and applications.  It wasn’t until the last few months that the recent versions of GNURadio worked through MacPorts.  Luckily it does now, as does all the BladeRF software.  Going from nothing to a working software environment took minutes.  One thing that you have to make sure and do it download the most recent FPGA code, as you’ll have to re-load it every time you boot the BladeRF.

All software defined radios have an Achilles’ heel.  If the DC offset of the I and Q baseband signals isn’t minimized a constant “tone” at zero Hz will be up-converted to whatever frequency the final spectrum is.  Also, if the relative magnitude and phase of I and Q aren’t matched (and precisely 90 degrees) there will be a image of the desired signal mirrored across the up-converter frequency.  The BladeRF wiki has a short article that shows how to measure the correction factors to use to minimize these effects.  This article documents my attempt of deriving the correction factors for one of the two boards.

To start, I tuned the board to 450MHz.  Then, I decided that a 100KHz sine would be appropriate as a baseband tone.  What happens is that, in software, the 100KHz tone is generated, then it is up-converted to 450.1MHz.  The spectrum below is the result of that test without any corrections applied.  The spur resulting from the DC error is about 25dB down from the desired carrier, and the image is closer to 35dB down.  It’s not really that great.

blade uncal

Playing around with the values according to the instructions, I was able to improve these results quite a bit.  The DC error is now 58dB down from the carrier (ignore the marker table) and the image is almost 63dB down.  This is pretty respectable.  Now, there is another troubling question.  What’s up with the spikes in the phase noise?


I asked on the #bladerf room on freenode, and they agree that it’s not normal.  The spikes are exactly 7.8 KHz apart, so I would start looking for things that happen at that frequency.  I wish I had measured how distant the largest one was from the carrier and zero.  That could have been good to know.

phase noise

Oh, wait, I did :).  The main tone is 63KHz away from the main carrier and 37KHz away from zero.  There was some speculation that it could be artifacts from the quantization of the software-generated sine wave or that the tuning algorithm could be at fault.  For fun, I ran the same test without generating any sine wave at all, so all you’re seeing is a large zero tone from a constant DC offset.  I do think that the quantization explanation makes sense because that would manifest as phase noise, and the spikes are centered about the modulated tone, rather than the zero-spur.

constThe same artifacts should still appear there if there was any kind of a problem with the power supplies of the board, for example.  It seems very clean, and I’m happy with the phase noise performance of the board.  You’re probably seeing the phase noise of the rigol in this plot rather than the BladeRF.

In all, so far, I’m very happy this these.  I’m very excited about their potential.


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Skyworks 65116 update

It has been a while since I played with the Sky65116 amplifier boards that I built and wrote about.  Since getting my own spectrum analyzer, I’m now able to make much better absolute measurements.  The DSA-815-TG analyzer is specified as having 1dB of uncertainly across the span, and the SA that I have at work is essentially uncalibrated.

Video modulator output

Video modulator output (click for enlargement)

Not only do I now know that the absolute power out of the video transmitter at the fundamental frequency is about 5.5dBm, I can also see the first and second harmonics.  I don’t know why I didn’t see them with the other analyzer, but they are disturbingly large.  I believe the FCC requirement is that these harmonics should be more than 40dB below the fundamental.  By this criterion, the transmitter should not even be sold in the US.

The SKY65116 amplifier has close to 36dB of gain, and a 1dB compression point of 32.5dB.  The 1dB compression point is specified as the output power level at which the gain is reduced by 1dB.  The easiest way to show this is with the graph from the Sky65116 data sheet, shown below.  You can see that as the output power begins to approach 32dB gain drops quickly.  The goal is to not force the amplifier to operate in this region.  If you do, you’re likely introduce harmonic distortion and other nasty nonlinear effects (i.e. intermodulation products).

Gain vs. Pout curve

Gain vs. Pout curve

So, knowing that the output is +5.5dBm, and we want about +30dBm out of an amplifier with a gain of 36dB, we need to introduce 11.5dB of attenuation (30dBm – 36dB – 5.5dBm = -11.5dB) between the transmitter and the amplifier, at a minimum.  It’s easy to make 14dB attenuators with standard value resistors (4×150 ohm and 1×120).  I’ve been playing around with QUCS a lot lately, so I’ve provided a model for the attenuator.  It’s just about the most boring S-parameter model you’ll ever see…  Perfectly flat response at -14dB, but that’s what we’re after.

Simple 14dB attenuator model

Simple 14dB attenuator model

A while back, I had a bunch of these simple 5-pole filter PCBs made up.  I just left them blank until I needed them, and I made two of them into 14dB attenuators using the circuit above.  I had two extra poles, so I filled one with a 0 ohm resistor and the other with a 1uF DC-blocking capacitor.  The capacitor reduces the low frequency performance, but only less than about 1.5MHz.  It’s worthy the trade-off in my mind.

Constructed attenuators

Constructed attenuators

I went ahead and covered one of the attenuators with copper sheet just to make it more of a completed package.  I’m sure I’ll need to use it many times in the future.  I left the other open so I could unsolder it and make it something else if needed.  An interesting thing happened when I installed the cover.  The small ripple in the attenuation (around 500 MHz, see below) occurred only after I installed the cover.  I assume this is due to parasitic capacitance between the components and the copper covering.  It’s still only about 1dB of ripple, so I’m satisfied with it.

14dB attenuator performance

14dB attenuator performance

Anyway, back to the amplifier.  I’ve now got about -8.5dBm going into the amp ( +5.5dBm – 14dB), so with its 36dB of gain, I should expect to see +27.5dBm out of the amp.  That’s getting very close to the maximum input power on my SA (+30dBm).  It’s always better to be safe with these things, so I used the other 14dB attenuator between the amp and the SA.  Now, I should expect to see +13.5dBm on the input.  I maxed-out the input attenuation on the analyzer (another 30dB) and gave it a shot.  Note that the internal attenuation is calibrated out of what’s shown on the display, and I told the SA about the other 14dB of attenuation, so the power values shown on the display are referencing the amplifier’s output.

Transmitter after amplification

Transmitter after amplification

In the above image, you can see that we’re getting 27.5dBm out of the amplifier!  I love it when a plan comes together!  This is the value I calculated, right on the nose.  I promise that I didn’t work the math backward! 🙂  Again, it’s so painfully obvious that the transmitter is AM, rather than the VSB signal that it should be.

Close-up of the signal

Close-up of the signal

Now, just for fun, let’s dive back into the video signal coming out of the transmitter.  In the image above, I’ve put some markers on the various carriers present in the signal.  The luma carrier is in the center at 433.85MHz, which is where we expect it to be.  Marker 2 is at 437.45MHz, which is 3.6 (let’s call it 3.57) MHz away, matching exactly where the chroma carrier is supposed to be.  There’s no audio carrier, which isn’t a surprise because there’s no audio, though I wouldn’t be surprised to see the carrier.  Marker 3 is 19 MHz away; I have no idea what this is or why it’s there.  It’s not supposed to be.  Same with marker 4.  Oh, well…  that’s what you get with a shitty transmitter.

amplifier gain v. frequency

amplifier gain v. frequency

Now, what about those pesky harmonics?  The Sky65116 is a 390-500 MHz amplifier, so my hope is that the reduced gain by the first harmonic will attenuate the harmonics enough to bring them into compliance.  The graph above is the gain v. frequency graph from the data sheet.  It’s neither encouraging nor discouraging.  It’s difficult to infer what’s going to happen at 800 MHz when the graph stops at 500 MHz.  In the image below, it appears that I lucked out.  The first harmonic is 42dB down from the fundamental.  If I were selling a product, there’s no way I would send this out for compliance testing.  It would just be too risky, I’m not that confident in my measurements.  By my math, it would cost less than $2 in parts (single unit quantities) to make a decent low pass filter.  That’s the right thing to do.  When I modeled it (in QUCS, again), I calculated that the harmonics would be within compliance even without the rolloff of the amplifier.  With the rolloff, the harmonics would be well below the noise floor.

Harmonics after amplification

Harmonics after amplification

I’ve had a ton of fun redoing this experiment with my new spectrum analyzer.  I’m going to write lots more about the analyzer in the future, and I’m really looking forward to it.  Coming soon is an exploration of the skyworks low noise amplifiers.  Between these two products, I expect to have a solid video link over 1000 feet or so.

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The enemy of any analyzer: Phase Noise.

That looks neat, but it’s very, very bad…

If there’s one thing that I was blissfully ignorant of before trying to build a spectrum analyzer, that is now an annoyance and borderline obsession, it’s phase noise.  Phase noise is exactly the same as any other kind of noise, but unlike noise on a DC signal, phase noise is mode like tiny variations in the frequency of the signal.

To get a little more specific, think about phase as a quantity that describes how far along the sine wave we are at any given instant.  It can be described in degrees, radians, or even if you’re a little radical, tau radians.  The idea is the same.  Phase increases until it “rolls over” at the end of the cycle.  It looks a bit like a sawtooth wave, assuming that we’re discussing a constant frequency, unmodulated wave.  Hopefully you believe me that phase noise looks just like noise superimposed on the sawtooth-shaped phase ramp.

Phase related to sine

I think the graphs above helps to illustrates the relationship between phase (above) and a sine wave (below).  I’ve re-scaled the phase so that it goes from zero to one over the range of one whole number.

In the frequency domain, phase noise is a little easier to understand, and see.  The graph at the head of this article is an extreme example of phase noise.  Really, there are two kinds of phase noise here, and one of them we can do something about.

PLL example (From a Linear Technology data sheet)

I tried really hard to find some nice graphics to use to describe, simply, the basic operation of a PLL-based oscillator.  The best I could come up with is the above diagram.  This was lifted from the Linear Technology LMX2326 PLL IC.  This is the same (or damn near) as the PLL chip that’s used in the analyzer.  The bottom left corner is the oscillator.  All it does it generate a single frequency set by the voltage coming into pin 6.  On the PLL chip, pin 2 is the output from the “charge pump,” which is how the PLL sets the tuning voltage.

PLO1 Schematic (by Scotty)

Unfortunately, the PLL in the spectrum analyzer isn’t this simple (if you can call an normal PLL simple!).  In the center, near the top, notice the Op-Amp.  The high-side supply to this amplifier is +20 volts (at least).  The reason for this is as simple as that’s what the VCO (voltage controlled oscillator) needs.  It isn’t possible for the PLL to produce voltages like this, so we need this extra supply.

VCO power supply noise

Now, the question is: “What happens when there’s noise on the +20 voltage supply?”  The waveform on the oscilloscope above shows about 20mV of noise on the 20 volt supply.  The frequency of this noise is about 20kHz. It’s no coincidence that the spacing between the peaks in the comb-like plot is about 20kHz.  What’s happening is that the noise on the 20 volt supply is literally modulating the output.  Incidentally, that’s exactly what you do if you want to frequency modulate something.

Now that we know what the cause is, what can we do about it?  If we eliminate that noise, we can fix the problem.  I had made a second 20 volt supply, and used cheap capacitors.  Apparently, when using high voltages (relatively speaking) the amount of capacitance decreases in cheap, small, ceramic capacitors.  I went back to the first supply I made, and added even more capacitance.

Better +20 volt supply

The lower trace is the new +20 volt supply, and it’s peak-to-peak noise voltage is about 3mV.  But the proof of the pudding is in the eating, so how does it affect the phase noise?

Much improved phase noise

It squashes it like a bug!  The above plot is almost textbook for phase noise.  The large peak in the center is representing the width of the final filter (I’ll get to that in a later post) and the skirt is caused by traditional phase noise.  If I zoom in to the center of that plot it’s easier to see:

close in phase noise

Here, I’ve highlighted another common cause of phase noise: PLL loop bandwidth.  This is the bandwidth of the filter that smooths out the pulses that come out of the PLL chip.

That’s all I have for now…  I’ve tried to make this topic, which is very technical and dry, interesting and accessible to those that haven’t spent the last 5 years trying to build a spectrum analyzer.  I hope you’ve enjoyed it.

If you want a much more in-depth and technical analysis, see Scotty’s website.


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Spectrum Analyzer Aluminum Frame

Beautiful new frame for my SA

I haven’t posted for a while.  I’m sorry.  I was being selfish.  I’ve made fantastic progress on my spectrum analyzer build, and it’s so much fun that I haven’t had the will to pull myself away and post about it.

Also, completely unrelated to the build, I’ve experimented with a service called “Cloudflare” as a way to make my site more resilient.  It doesn’t, it’s MUCH worse.  I’m not happy with it at all.  I’ve shut it down, so hopefully once the DNS changes propagate it’ll be more stable.

Anyway, back to topic.  The last post about the analyzer was about the ChipKit digital logic controller.  That was going very well, so well, in fact, that I was able to finally diagnose an intermittent connection problem between modules.  Intermittent problems are always the worst, especially when you don’t trust other components in the system.  The reason this is relevant to the discussion at hand is that the problem only manifests when one of the connectors has pressure one one side.  I needed a reliable way the hold all the modules in fixed positions.

Since beginning this project, I’ve been inspired by the way that two people built their analyzers. Hans’ is probably my favorite.  I took the image below from his photo album in the Yahoo Spectrum Analyzer group.

Hans’ analyzer “bottom view”

I love how clean and organized it looks.  Much different than most of the others out there.  His frame has holes that go all the way through the frame, and he has a back cover that screws on.  His coax cabling is made of right-angle soldered-on connectors with what looks like RG-405 hard pipe.

Another inspirational build is Sants.  This image is also scraped from the Yahoo group.

Sant’s build

This build is most probably the closest to mine.  The pockets, or wells, for the component side of the boards don’t go all the way through the substrate.  Notice, in both designs, that there is a small lip around the perimeter of each well.  This is there to hold the boards and to electrically connect to the ground vias on the perimeter.  This design also uses right-angle connectors and hard pipe.

With these designs in mind, I sought out the things I would need.  First, of course, was the aluminum itself.  I had looked into McMaster-Carr (hopefully this link works), and a 1/2″ thick 12″ square costs about $40.  Then, my brother suggested looking on eBay.  I was able to find an equivalent sheet for about $30 after shipping.

Frame block layout

Once I had a cool hunk of 6061 alloy in my hands, I started designing the layout of the frame.  I started with OmniGraffle (it’s like Visio) because I could lay it out to scale, and the connections move in a natural way.

Once the layout was complete, I transcribed the design, complete with all the details into AutoCAD.  By this time, about a month passed, and I was able to find someone willing to machine it for me as a favor.  I also got a quote from another friend, which was about $250.  This is a reasonable cost for something like this, in case you’re looking to duplicate my results.

Close up of one of the wells

It took several weeks to get the parts back from the machinist, but the results are totally worth it!  The larger hole was cut with a 1/8″ end mill, and the inner pocket was cut with a 1/4″ mill.  With the majority of the modules, the inner radius is fine.  There were a few exceptions, however.

Small relief for DDS capacitors

This photo shows some of the rework I had to do to accommodate a few capacitors right at the edge of the DDS module.  It’s very difficult to take a picture of a small notch in a shiny material, but hopefully you can see the cut into the side of this pocket.  I made that mostly by making small, successive cuts using an exact-o knife.  The PLO reliefs were a bit more aggressive (there is a power header right in the corner), so I had to use a Dremel cutter bit in my drill press.

Relief for the PLO module

Once important lesson learned in this process is that 1.2″ or 2.4″ set into a PCB specification is more of a suggestion rather than something that you can count on all that much.  I had to sand almost every module to get it to fit.  Once that was done, however, everything fit like a glove.

Making custom coax jumpers

The final piece in the puzzle is the coax.  The perfect jumpers that both the other designs featured were definitely something that I wanted.  It’s possible to get these right-angle SMA connectors from China for about a dollar a piece, much less than the ~$5 that you’ll spend at Digi-Key.

Connector end, ready for solder.

To make them, all you really need to do is measure the coax sections, strip the ends, and solder…

Soldered center conductor

Soldering around the shield of the coax is the hardest part, and it’s not even that bad.

Final product!!

That’s all there is to it!  I’m really happy with how well things turned out.  Certainly something to be proud of.  Over the next few days, I’m going to try to keep posting about the other advancements.  I have a bit of a backlog, so I should be able to keep them coming…

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More ChipKit spectrum analyzer progress

Modifications to the ADC

I’ve been able to make solid progress on the spectrum analyzer tonight.  I’ve continued using the ChipKit, I’m fairly happy with it at the moment.  As I mentioned in the last post, I’ve increased the baud rate on the serial port to 115200 baud.  That seems to be the point where the SPI bus speed and the serial port speed are about matched.  There’s still plenty of room to increase it, however.

I’ve been progressing in the project by adding one module at a time, and testing as best I can.  I’ve got PLO2 (mostly) working, and DDS1 seems to be rock-solid.  I’m able to command it to any frequency I want between almost 0 Hz up to 20 MHz.  Tonight, I added the ADC to the list of modules that seem to be working.  To accomplish this, I had to make two modifications to the ADC.  The first was to change it to work with a 3.3v DC supply.  This change was trivial, it’s the same as the modification to run off of the power from the PDM.  You just remove the old voltage regulator and replace it with a bit of wire.  This is necessary because, if it’s powered with 5 volts, the minimum voltage required to mark a digital ‘1’ is 3.8 volts.  The PIC32 in the chip kit is powered by 3.3 volts, so there’s no way that’s going to happen.  In reality, it’s probably going to work, but it’s likely going to give you a headache.  Finally, I removed the two transistors that were on the outputs of each ADC.  They were there to provide stronger output drivers (the ADCs can only drive their outputs with 500uA).  The parallel port requires a pretty healthy amount of current on the status lines.  Because it’s being connected directly to a micro controller, these drivers aren’t necessary.  Not only that, but they were acting as it they were damaged.  With them gone, everything seems to work great!

Now that the ADC and a DDS works, I can begin to use it as a spectrum analyzer… even if it’s only for a very small range of frequencies.  For example, I can make a plot of the filter used with the “squarer” in the DDS:

DDS1 squarer response

It’s not immediately clear whether this plot makes any sense, I’m hoping that I can get someone in the panel of experts to weigh in on it.  It’s reasonable clear that there is a pass band centered around 10.7 MHz, which is what I want.  I’m not sure what to think about those steep slopes and the large spike of to the right.  None of this may matter, as the DDS will never be tuned out there anyway.  It could even be that a harmonic of the DDS output is getting through the passband when it’s tuned there.  I really have no idea.

The plot below is from the final resolution bandwidth filter (RBW) that’s used to set the resolution of the analyzer as a whole.  I got this filter from one of the MSA experts (thanks, Sam), and I know it performs better than this.  Again, I’m wondering if it has this shape due to some quality of the DDS output, or some other factor.

Shape (maybe) of my final resolution bandwidth filter

Ultimately, I think these graphs are great, and very encouraging.  Even if they’re a bit confusing, it’s nice to be able to put something up on the screen.  You might be wondering how I produced them?  Well, that’s the embarrassing bit.  My cheesy analyzer program (which is really just a way to test the suite of classes I’ve written for communicating with the modules) will spit out text that can be used as a CSV (comma separated values) file that can be read by Excel or Numbers.  I used Numbers to create these plots.  I think they’re log-scale plots, because the log detector module produces logarithmically increasing voltage given increasing input power, thus I used linear scaling on the Y axis.  The Y axis is the raw value from the ADC, and the X axis is the frequency.


I got an email back from Scotty about the graphs I got from my DDS sweeps.  The first plot, of the DDS squarer, is normal.  The reason it has that shape is best explained in the context of the schematic of that part.

DDS Squarer (section of the schematic from scotty’s webpage)

Trace the signal from “OUTA,” it goes through matching network (I think!), then a crystal filter (XF1), and a logic inverter.  Basically, the inverter will “snap” on or off once the sine wave from the filter passes a threshold voltage.  Once the signal is attenuated to a certain level by the crystal filter, the inverter will no longer trigger.  This is the reason for the sharp skirts on either sides of the passband.

Scotty also thinks that the response plot from the RBW filter is indicative of a mismatched input or output.  I’m pretty sure it isn’t the actual filter, so I’m going to look into other sources of impedance mismatch.

Update 2:

Not only did Sam agree that the shape of the RBW filter is likely due to the impedance mismatch between the source and the filter, but that I could probably help the situation with an attenuator.  I inserted one (with a DC blocking capacitor) between the DDS source and the filter, the plotted it again.

Second plot of the filter shape

My only concern now is that the filter bandwidth looks much much wider than I expected.  I don’t know what the cause of this is.  Because I really have no calibration, I don’t know how the “counts” in the ADC map to dBs of signal.  Typically, filters are defined by the points to the right and left of the center that are 3dB “down” from the center level.  However, I may be able to glean some knowledge from the datasheet.

RSSI voltage vs. input power level (from the Analog devices datasheet)

The slope is ROUGHLY(!) a half a volt per 20dB.  I’ll do a better calibration when the code is there, but for now let’s just continue on.  Once we know what the slope is, we need to map the counts on the ADC output to volts.  I’ve converted the ADC to use 3.3volt power, and it’s a 16 bit device, so there are 65,536 counts (numbers) spanning 3.3 volts, or 19859 counts per volt.  In my spreadsheet, I just made a new column that performs this conversion.  Finally, because it looks like 2 volts maps to about 10dB.  So, I added another column to the spreadsheet, this time subtracting 2 from the volts, divide by .5 and multiply by 20.

Unfortunately, it’s not easy to see where the 3dB points are.  Looking at the raw data, I can see that the maximum value is -13.0 dB, so the 3dB points are where -16.0 dB is crossed on each side.  On the low side, it’s 10.6989, and on the high side, it’s 10.701360.  The resulting 3dB bandwidth is .002 MHz, or 2 kHz.  This is exactly the published value.  I guess this means that it was a very successful experiment.